RTL Development Engineer trainee


Open positions & working at AImotive

Location: Budapest, Hungary

RTL Development Engineer trainee

We are looking for enthusiastic students for the RTL design engineering position in our Budapest office. The task is part-time hardware development in SystemVerilog language.

By accepting our offer, you'll have the opportunity to

  • Understand the digital ASIC design process through real industry related tasks
  • Master the steps for optimal RTL code design for both ASIC and FPGA platforms
  • Participate in the implementation of neural networks
  • Gain implementation practice in high performance computing
  • Gain proficiency in the optimization of power consumption and clock signal frequency of completed RTL specifications
  • Gain experience in designing for a safety-critical application area (self-driving car / satellite)


  • Participation in research and development of a neural network accelerator chip
  • Implementation of functional units in SystemVerilog language
  • We provide the test environment for your module

Key Qualifications

  • Ongoing university studies 
  • Flexibility, effective and efficient teamwork
  • Reliable and quality oriented attitude

What We Offer

  • Part-time job opportunity (approx. 20 hours/week), flexible working hours
  • Competitive student salary
  • You can be a part of a supportive, senior professional team
  • Inspiring and helpful environment
  • Possibility of an immediate start
  • Teambuilding events and other benefits for students
  • Free lunch every workday at one of the best all you can eat restaurants in Budapest
  • Fitness opportunities

Apply for this position