The aiWare IP core can be configured to implement a variety of ASIL-D capable configurations. These are based on a range of lockstep-based redundancy schemes at ALU, block or ring level, with optional ECC memories. The architecture has been refined over the past four years using AImotive’s HD versions of industry-standard benchmarks, alongside aiDrive™, AImotive’s self-driving software stack, tested continuously in our fleet of test vehicles around the world. This means that the aiWare architecture was designed against tests run on realistic self-driving system designs, not only against isolated benchmarks. AImotive’s many years’ experience in developing embedded processing benchmarks ensures that these results are trustworthy and repeatable.
The aiWare3 core can deliver more than 2 TMAC/s per W (4 TOP/s per Watt – 7nm estimated) while sustaining >95% efficiency under continuous operation. Though many NN accelerators claim superior power consumption and performance, this is often when running their accelerator under ideal simulated conditions. These simulations only measure the power consumption of the core itself. Unlike other solutions, aiWare3’s architecture has been optimized to deliver the highest efficiencies when integrated into realistic production ECU designs. The low latency and deterministic behavior of aiWare enables hardware platforms prepared for the real-world challenges of the production of autonomous vehicles providing high-performance low-power, small size ECUs.
Building on the award-winning aiWare2 core, aiWare3’s highly configurable and scalable architecture enables OEMs to implement a variety of NN acceleration strategies in their hardware platforms. These can range from centralized NN resources shared among multiple workloads as part of a powerful central processing unit, to pre-processing integrated into each sensor or groups of sensors. Using aiWare OEMs have far greater choice in the way they approach production AV timescales, by shrinking the size of ECUs needed to support high-performance NN processing. The highly autonomous accelerator-based approach used by aiWare also enables customers to maximize the re-use of their significant investment in existing hardware and software designs.
The new aiWare3 IP core extends the outstanding performance and configurability of the aiWare v2 core. Adding aiRing™, a highly optimized hierarchical ultra-high bandwidth ring bus structure. Because aiWare3 uses the same computation core as aiWare v2, the aiWare IP core portfolio now offers a highly scalable solution from 1 INT8 TMAC/s to more than 50 INT8 TMAC/s (>100 TOPS) per chip. All solutions are supported by the same software APIs and SDK. Thanks to the unique low-level control structure that involves no caches or programmable cores, aiWare3 is also far more deterministic in its operation than other more programmable approaches. This makes aiWare one of the most flexible solutions for the production of highly autonomous vehicles.Contact for More Info