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Building Blocks

aiWare Building Blocks


  • Optimized for multiple high-resolution sensor applications
  • Scalable, configurable, low latency, high efficiency, architecture
  • Performance up to >50 TMAC/S with clock speeds up to 1GHz
  • Optimizes use of local DDR and on-chip memory for efficiency
  • Patented data management for automotive inference workloads
  • Comprehensive SDK includes tools to convert FP32 NNs to INT8


  • Enables integration within SoCs or dedicated accelerators
  • Support several ASIL-B (v2) and ASIL-D (v3) compliant solutions
  • Ideal for NN processing in camera, LiDAR or radar subsystems
  • Highly autonomous NN processing maximizes host offload
  • Khronos® NNEF allows NN import from several AI/ML frameworks
  • Application agnostic – accelerates any NN

Built for Automotive

The aiWare IP core can be configured to implement a variety of ASIL-D capable configurations. These are based on lockstep-based redundancy schemes at ALU, block or ring level, with optional ECC memories. The architecture was designed against tests run on real self-driving systems, not only isolated benchmarks. AImotive’s experience in developing embedded processing benchmarks ensures that these results are trustworthy and repeatable.

Unmatched Power Efficiency

The aiWare3 core can deliver more than 2 TMAC/s per W (4 TOP/s per Watt – 7nm estimated) while sustaining >95% efficiency under continuous operation. The architecture has been optimized to be most efficient when integrated into production ECU designs. Its low latency and deterministic behavior enable hardware platforms prepared for the challenges of production autonomous vehicles providing high-performance low-power, small size ECUs.

Flexible Performance

The aiWare3 architecture enables a variety of NN acceleration. These can range from centralized NN resources to pre-processing integrated into each sensor. Using aiWare OEMs have greater choice in their production AV timescales, by shrinking the ECUs needed to support NN processing. aiWare3’s highly autonomous accelerator-based approach also enables the maximized re-use of our partners’ investment in existing hardware and software designs.

aiWare™2 Plus aiRing

The aiWare3 IP extends the performance of aiWare2, by adding aiRing, a hierarchical ultra-high bandwidth ring bus structure. The aiWare IP core portfolio thus offers a highly scalable solution from 1 INT8 TMAC/s to over 50 INT8 TMAC/s per chip, all supported by the same software APIs and SDK. Utilizing a low-level control structure without caches or programmable cores, aiWare3 is more deterministic in operation than programmable approaches.