Hardware IP for Automotive AI

aiWare4: advanced wavefront processing, upgraded safety and low-power features

The 4th generation of aiMotive's aiWare NPU hardware IP builds on the ultra-high efficiency architecture of aiWare3, extending performance and scalability both at the high end (up to 256 TOPS per core) and at the low end. Featuring substantial upgrades to on-chip memory architecture, innovative new wavefront-processing algorithms and enhanced ISO26262-compliant safety features, aiWare4 delivers the ultimate scalable solution from the most challenging single-chip edge applications to the highest performance central processing platforms for automotive AI. With aiWare4 many key metrics have been further improved, including TOPS/mm2, effective TOPS/W and support for wide range of automotive NN types beyond CNNs including Transformer Networks, LSTMs, RNNs. With aiWare4, the ultimate automotive NPU has arrived!


Up to 256 TOPs per core (up from 32 TOPS for aiWare3) with greater configurability of on-chip memory, hardware safety features and external/shared memory support


Enhanced standard hardware features and related documentation ensuring straightforward ISO26262 ASIL B and higher compliance for both SEooC (Safety Element out of Context) and in-context safety element applications

Power, Performance and Area (PPA)

8-10 Effective TOPS/W for typical CNNs (theoretical peak up to 30 TOPS/W) using a 5nm or smaller process node; up to 98% efficiency for a wider range of CNN topologies; more flexible power domains enabling dynamic power management able to respond to real-time context changes without needing to restart


Innovative Wavefront RAM (WFRAM) leverages aiWare’s latest wavefront-processing and interleaved multi-tasking scheduling algorithms, enabling more parallel execution, better multi-tasking capability and substantial reductions in memory bandwidth compared to aiWare3 for CNNs requiring access to significant external memory resources 


aiWare4 extends aiMotive’s leadership with up to 98% efficiency over a wider range of NN topologies. This efficiency scales especially for large input sizes such as early fusion of multiple different high data rate sensors, or from one or multiple high resolution camera sensors
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