Location: Budapest, Hungary / Posted at: 9/22/20
Design Verification Engineer
Job Summary
- Define coverage and coverage goals from hardware specification
- Implement testbenches that employ black box, white box and constrained random techniques
- Engage in functional simulation and debug of new RTL features
- Author test plans and write tests that participate in full design regressions
Key Qualifications
- BSc/MSc in Mathemathics/Engineering
- Experience with embedded software development (C, C++)
- Knowledge of Verilog language
- Basic knowledge of computer architecture and digital design
- Strong abstraction skills
- Strong English knowledge (at least in reading/writing)
Considered as a plus
- Experience in ASIC or FPGA design
- Experience in SystemVerilog Assertions (SVA)
- Proficiency in Vera, e, SystemC languages
- Proficiency in OVM/UVM verification and simulators
- Knowledge of developer tools and script languages (Git, Bash/Shell, TCL, etc.)
What We Offer
- The opportunity to solve difficult problems with immediate real-world applications
- Competitive salary, share option and fitness opportunities
- Work on the hottest applied research problem
- Opportunity to work with the leading Automotive and Tech companies on industry disrupting technologies
- Visit relevant international conferences
- We believe: people over process, we are keen to maintain work-life balance